The Queue
How AI Split Memory Into a Protected Tier and a Residual Market, and Why Physical Scarcity May Outlive Producer Rent
By Shanaka Anslem Perera
July 23, 2026
The most important number in the 2026 memory market is not 98 percent. It is 13 to 18 percent.
The first records the violence of the broad first-quarter repricing. The second captures a different fact: by the third quarter, several large United States cloud providers were protected by multi-year agreements that limited further repricing. The figures are not a like-for-like spread across product and time. Their coexistence shows that one physical shortage had begun producing different contractual economics. That divergence is the queue.
The queue is the part of the memory crisis that the market has not fully named. Memory has not stopped clearing by price. Price still matters, often violently. But price no longer decides allocation alone. Contract, qualification, product generation, delivery priority, legal admissibility, and the willingness to finance future capacity now determine who receives what, when, and on which terms.
That distinction divides one apparent supercycle into two different assets.
The first asset is physical scarcity. It is governed by cell physics, cleanroom capacity, process migration, yield, packaging, qualification, power, and the years required to turn a construction site into accepted commercial output.
The second asset is scarcity rent. It is governed by price bands, customer bargaining power, the share of supply already reserved, competition in the residual market, political tolerance, and what happens when long-term agreements meet their first real downturn.
Those clocks can separate. The shortage can persist after margin growth peaks. Supplier earnings can remain protected while customer credit weakens. Public prices can fall while contracted economics remain firm. New physical capacity can arrive without being qualified for the buyer who needs it. Global output can rise while trusted supply remains scarce.
The result is a market that can be tight and normalizing at the same time.
That is the central institutional discovery. Long scarcity is not long rent. AI underwrote the queue, not the peak margin.
The Price Signal That Could Not Summon Supply
Why the Price Signal Failed
A normal commodity shock contains the mechanism of its own destruction. Price rises. Producers expand. Buyers substitute. Inventories rebuild. The marginal unit becomes less valuable, and the cycle turns.
Memory has followed that sequence often enough to train an entire generation of investors into reflex. A shortage was simply a future glut waiting for enough capital and enough time.
The 2026 episode is different in one specific respect. The price signal became extraordinary before the physical response did. TrendForce measured conventional DRAM contract prices rising 93 to 98 percent in the first quarter and forecast another 58 to 63 percent in the second. It forecast NAND contract pricing up 70 to 75 percent in the second quarter. Yet the same research described 2026 output growth as dependent mainly on process migration and manufacturing optimization, with limited expansion in wafer input.
The second-quarter figures are forecasts, not a universal realized index. The products, customers, and contract dates differ. But the directional fact is not in dispute. Prices moved far faster than the industry’s publicly disclosed supply response.
The popular explanation begins with allocation. Three companies controlling almost nine-tenths of global DRAM revenue shifted scarce resources toward server products and high-bandwidth memory because those products offered superior strategic value. That is true as a description of what happened at the margin. It is incomplete as an explanation of why the price signal could not call forth enough new supply.
Margins explain which product receives an existing wafer. They do not explain why additional qualified wafers cannot appear quickly.
The real anomaly is not that AI buyers moved to the front. It is that the line could not lengthen fast enough behind them.
The Capacitor Wall
A conventional DRAM cell contains one transistor and one capacitor. The capacitor stores electrical charge. The transistor controls access to it. The cell must preserve enough charge, for long enough, to distinguish a one from a zero before the next refresh.
For decades, the industry increased supply largely by shrinking that cell. A smaller cell placed more bits on the same wafer. Process migration delivered capacity without a proportionate increase in cleanroom area. That was the hidden elasticity behind the old memory cycle. New bits arrived from better geometry as well as from new factories.
That mechanism has weakened.
Imec, one of the world’s leading semiconductor research institutions, says DRAM scaling, cost, and power efficiency have struggled to keep pace since about 2015. The large capacitor constrains both cell scaling and three-dimensional integration. As the access transistor shrinks, leakage becomes more difficult to control, reducing retention time and increasing refresh demands.
Applied Materials describes the problem from the factory floor. The storage capacitor is roughly 30 nanometers in diameter. As that diameter falls, the structure must become taller to preserve capacitance. The resulting holes become harder to etch, coat, and keep mechanically uniform. A process improvement can extend the roadmap. It does not restore the old economics of effortless density growth.
